1. Technical Field
This invention generally relates to clock signals in electronic systems and more specifically relates to a design structure for dynamic clock phase alignment between independent clock domains.
2. Background Art
Most computer and other electronic systems use synchronized logic to analyze, store and transmit data. Synchronized logic systems have one or more clock signals that are used to keep the logic synchronized. The “clocks” or clock signals are used to latch data or activate logic components. The clock signals are most often an oscillating square wave signal, or at least close to a square wave. The activation of logic components by the clock signal is most often done on the rising or falling edge of the clock signal.
In many computer and electronic systems there are high speed data links and other links that pass signals from one clock domain to another. Each of the clock domains are synchronized by different clock distribution networks where each of the clock distribution networks is typically a set of related clocks. The phase relationship of the clocks in the separate domains is sometimes unknown due to spatial separation of the clock domains or because different logic families are used to generate the clock networks. Another possible reasons for phase difference is the amount of logic in the clock path from the oscillator that increases the clocks sensitivity to voltage and temperature differences.
In some prior art systems with asynchronous clocks, data is aligned to clock boundaries using multiple latches that insure the data is latched properly across the asynchronous boundary. Other prior art systems use handshaking signals or FIFOs (first-in-first-out buffers) to synchronize data between clock domains. These common prior art solutions introduce a significant delay in the data stream. Without a way to more efficiently align clock signals in dependent clock domains, the computer industry will continue to suffer from clock latency and inefficient alignment of the clocks of independent clock domains.